SPI Master Interface Project

Logical Design II

		Students: Leonardo Vidal Paolo Rotela Faculty: Julio Pérez Javier Rodríguez

Main Goals

A "SPI" system consists of "master" and one or more "slave" type systems exchanging data accross a serial connection. The "master" device is responsible of clock generation while all the slaves use that clock. There are four basic signals : MOSI (Master Output/Slave Input), MISO (Master Input/Slave Output), SCK (Serial Clock) and SS (Slave Selector). All data transferred is synchronized using the clock signal provided by the Master device. The most significant bit is always sent first.

Our project main is goal was to implement a master SPI system using VHDL, and to realice this design using a EPF10K20RC240-4 device from Altera. Our design was to have a parametrized amount of SPI slaves and also a parametrized maximum word length.

Design

As a result of our work, two different implementations were found to be needed depending on the concrete realworld application:

"Flexible:"

This implementation is dynamically configurable. In this scenario, those peripherals connected to the master system change or change their characteristics in such a way that it is not possible to include their configuration at compile time. This module has internal registers that store each slave's different configurations. In this way, interface characteristics can be changed by modifying a register's value in order to allow the master device to meet the changing slave's new configuration.

"Rigid:"

This implementation is only configurable statically. In this case, all peripheral configuration is determined trough constants defined in source code. Once compiled and hardware built, it is not possible to modify the peripheral's characteristics. Peripheral characteristics can only be changed by the reprogramming of the logical device. This implementation is more economical in terms of logic elements (e.g. flip-flops are not needed) than the Flexible case. It also uses less signals in its user-module interface.
 

Main Characteristics

The number of slave devices that the master system can handle is given by a parameter (GENERIC VHDL). According to this value, the interface has a register associated to each device. This register stores all the characteristics each slave device needs. In each of these registers one can configure:

Phase and Polarity

They are related with the synchronization between the transfer clock and data.

Transfer Speed

A transfer speed can be selected from a certain set of calues. These values are powers of two with respect of input frequency.

Active Select Level

The active select level for each device can be individually specified.

Word Width

Word length can be selected for each device. Word length equals the number of bits transmitted in each transfer.

By using other parameters it is possible to determine the range of variation of some of these fields. In other words, the number of bits reserved for each field is configurable. In this way, the range of action of each of those parameters is also affected. For example, there is a parameter that allows one to select the amount of bits for the selection of transfer speed. By modifying this value, the amount of different selectable speeds and their range is also modified. There is another parameter for the range of possible word lengths.

Files

Documentation and VHDL sources can be found here.