Arquitectura integrada de consumo eficiente para aplicaciones de registro de señales neurales sensibles al CMRR (Current efficient integrated architecture for common mode rejection sensitive neural recordings)
Julián Oreggioni
PhD thesis from Universidad de la República (Uruguay). Facultad de Ingeniería. IIE - Mar. 2018
Advisor: Fernando Silveira
Co-advisor: Angel Caputi
Research Group(s): Microelectronica (gme)
Department(s): Electrónica
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Resumen

In the last decade we have seen a significant growth of research and potential applications of electronic circuits that interact with the nervous system, in a wide range of applications, from basic neuroscience research to medical clinic, or from the entertainment industry to transport services. The real time acquisition and analysis of brain signals, either through wearable electroencephalography (EEG) or invasive or implantable recordings, in order to perform actions (brain machine interface) or to understand aspects of brain operation, has become scientifically and technologically feasible. This thesis aims to support neural recording applications with low noise, currentefficiency and high common-mode rejection ratio (CMRR) as main features of the recording system. One emblematic example of these applications in the neuroscience domain is the weakly electric fish neural activity recording, where the interference produced by the discharge of the fish electric organ is a key factor. Another example, from the implantable devices domain, is the nerve activity recorded with cuff electrodes, where the desired signal is interfered by electromyographic potentials generated by muscles near the cuff. In these cases, the amplitude of the interfering signals, which mainly appear in common mode, is several orders of magnitude higher than the amplitude of the signals of interest. Therefore, this thesis introduces a novel integrated neural preamplifier architecture targeting CMRR sensitive neural recording applications. The architecture is presented and analyzed in depth, deriving the preamplifier transfer function and the main design equations. We present a detailed analysis of a technique for blocking the input dc component and setting the high-pass frequency without using MOS pseudo-resistors. One of the main contributions of this work is the overall architecture coupled with an efficient and simple single-stage circuit for the preamplifier main transconductor. A fully-integrated neural preamplifier, which performs well in line with the state-ofthe-art of the field while providing enhanced CMRR performance, was fabricated in a 0.5 um CMOS process. Results from measurements show that the measured gain is 49.5 dB, bandwidth ranges from 13 Hz to 9.8 kHz, CMRR is very high (greater than 87 dB), and it is achieved jointly with a remarkable low noise (1.88 uVrms) and current-efficiency (NEF = noise efficiency factor = 2.1). A second version of the preamplifier with one external capacitor achieves a high-pass frequency of 0.1 Hz while keeping the performance of the fully-integrated version. In addition, we present in-vivo measurements made with the proposed architecture in a weakly electric fish (Gymnotus omarorum), showing the ability of the preamplifier to acquire neural signals from high amplitude common mode interference in an unshielded environment. This was the first in-vivo testing of a neural recording integrated circuit designed in Uruguay done in a local lab. Furthermore, signals recorded with our unshielded low-power battery-powered preamplifier perfectly match with those of a shielded commercially-available amplifier (ac-plugged, without power restrictions). To the best of our knowledge, the proposed preamplifier is the best option for applications that simultaneously need low noise, high CMRR and current-efficiency. Furthermore, in this thesis we applied the aforementioned architecture to bandpass biquad filters, specially but not only, to those with differential input. The new architecture provides a significant reduction in consumption (up to 30%) and/or makes it possible to block a higher level of dc at the input (up to the double, without using decoupling capacitors). Next, we applied the novel architecture to the design of the different stages of an integrated programmable analog front-end. Results from simulations shows that the gain is programmable between 57 dB and 99 dB, the low-pass frequency is programmable between 116 Hz and 5.2 kHz, the maximum power consumption is 11.2 uA and the maximum equivalent input-referred noise voltage is 1.87 uVrms. The comparison between our front-end and other works in the state-of-the-art shows that our front-end presents the best results in terms of CMRR and noise, has the greatest value of gain and equals the best NEF reported. Finally, some system-level topics were addressed during this thesis, including the design and implementation of three prototypes of end-to-end wireless biopotentials recording systems based on off-the-shelf components. Developing and applying circuits, systems and methods, for synchronized largescale monitoring of neural activity, sensory images, and behavior, would produce a dynamic picture of the brain function, which is essential for understanding the brain in action. In this context, we hope that the present thesis become our first step to further contribute to this area.

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